`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/07/07 16:26:33
// Design Name: 
// Module Name: compile_time_test_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module compile_time_test_top(
    input	wire					local_clk_100mhz	
);




localparam  FPGA_CODE_VERSION  =   "FPGA_CODE_VERSION 1.0.00.xxxx001"; // 注意长度应该为32个字节(256bit)




wire            clk_100mhz;
wire            clk_locked;
mmcm_system_clock mmcm_system_clock_inst(
    // Clock out ports
    .clk_out1   (clk_100mhz         ),     // output clk_out1
    // Status and control signals
    .locked     (clk_locked         ),       // output locked
    // Clock in ports
    .clk_in1    (local_clk_100mhz   )      // input clk_in1
);



wire            reset;
assign reset = ~clk_locked;


fpga_version #(
    .FPGA_CODE_VERSION(FPGA_CODE_VERSION)
) fpga_version(
    .clk    (clk_100mhz     ),
    .reset  (reset          )
);




endmodule
